 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| HT46R322/HT46R342 A/D with OPA Type 8-Bit OTP MCU Technical Document * Tools Information * FAQs * Application Note - HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM - HA0049E Read and Write Control of the HT1380 - HA0051E Li Battery Charger Demo Board - Using the HT46R47 - HA0052E Microcontroller Application - Battery Charger - HA0083E Li Battery Charger Demo Board - Using the HT46R46 Features * Operating voltage: * Up to 0.5ms instruction cycle with 8MHz system clock fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V * 36 bidirectional I/O lines (max.), including 16 LED at VDD=5V * 6-level subroutine nesting * 4 channel 12-bit resolution A/D converter * Integrated single operational amplifier or comparator driver with twice sink/source current * Single interrupt input shared with an I/O line * 8-bit programmable timer/event counter with overflow selectable via configuration option * Dual 8-bit PWM outputs shared with I/O lines * Bit manipulation instruction * Full table read instruction * 63 powerful instructions * All instructions executed in one or two machine interrupt and 7-stage prescaler * Integrated crystal and RC oscillator * Watchdog Timer * 204814 Program Memory capacity - HT46R322 409615 Program Memory capacity - HT46R342 * 888 Data Memory capacity - HT46R322 cycles * Low voltage reset function * 44-pin QFP package 1928 Data Memory capacity - HT46R342 * Integrated PFD function for sound generation * Power-down and wake-up functions reduce power consumption General Description The HT46R322 and HT46R342 are 8-bit, high performance, RISC architecture microcontroller devices. With their fully integrated A/D converter they are especially suitable for applications which interface to analog signals, such as those from sensors. The addition of an internal operational amplifier/comparator and PWM modulation functions further adds to the analog capability of these devices. With the comprehensive features of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, multi-channel A/D Converter OP/Comparator, Pulse Width Modulation function, Power-down and wake-up functions etc, the application scope of these devices is broad and encompasses areas such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. The HT46R342 is under development and will be available soon. Rev. 1.00 1 December 21, 2006 HT46R322/HT46R342 Block Diagram P A 5 /IN T In te rru p t C ir c u it STACK P ro g ra m ROM P ro g ra m C o u n te r IN T C TM RC TM R P A 3 /P F D In s tr u c tio n R e g is te r M U X PA4 M U X fS YS P r e s c a le r P A 4 /T M R fS YS MP M U X DATA M e m o ry W DT /4 W DT OSC PEC PE In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r PA3,PA5 PCC PC OSC2 OS RE VD VS S S D C1 ACC LVR MUX PW M PDC STATUS PD P o rt E PE0~PE7 P o rt D P D 0 /P W M 0 P D 1 /P W M 1 PD2 PD3 P o rt C PC 0~PC 7 4 -C h a n n e l A /D C o n v e rte r PBC APN APP APO L o w O ffs e t O P -a m p PAC PA P o rt A PA PA PA PA PA 0~P 3 /P 4 /T 5 /IN 6~P A2 FD MR T A7 PB P o rt B P B 0 /A N 0 ~ P B 3 /A N 3 PB4~PB7 Rev. 1.00 2 December 21, 2006 HT46R322/HT46R342 Pin Assignment PE PE PE PE PE PE PE PA PA P A 5 /IN P A 4 /T M R 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 T 6 PE PC PC PC PC PC PC PC PC 0 7 6 5 4 3 2 1 7 7 6 5 4 3 2 1 PA3 PB3 PB2 PB1 PB7 PB6 PB5 PB4 /P F D PA2 PA1 PA0 /A N 3 /A N 2 /A N 1 33 32 31 30 H T 4 6 R 3 2 2 /H T 4 6 R 3 4 2 4 4 Q F P -A 29 28 27 26 25 24 23 0 OSC2 OSC1 VDD RES P D 0 /P W M 0 P D 1 /P W M 1 PD2 PD3 VSS APP APN APO P B 0 /A N 0 Pin Description Pin Name PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6, PA7 PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4~PB7 I/O Options Pull-high Wake-up PA3 or PFD Description Bidirectional 8-bit input/output port. Each pin can be configured as wake-up input by configuration options. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have pull-high resistors. The PFD, TMR and INT pins are pin-shared with PA3, PA4 and PA5, respectively. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins PB0~PB3 are pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor are disabled automatically. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A configuration option determines if all pins on the port have pull-high resistors. Bi-directional 4-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on this port have pull-high resistors. PD0/PD1 are pin-shared with the PWM0/PWM1 outputs selected via configuration option. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A configuration option determines if all pins on the port have pull-high resistors. APO, APN and APP are the internal operational amplifier, output pin, negative input pin and positive input pin respectively . Schmitt trigger reset input. Active low. Positive power supply Negative power supply, ground. OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. I/O I/O Pull-high PC0~PC7 PD0/PWM0 PD1/PWM1 PD2 PD3 PE0~PE7 APO APN APP RES VDD VSS OSC1 OSC2 I/O Pull-high I/O Pull-high PD0 or PWM0 PD1 or PWM1 I/O O I I I 3/4 3/4 I O Pull-high 3/4 3/4 3/4 3/4 Crystal or RC Rev. 1.00 3 December 21, 2006 HT46R322/HT46R342 Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter VDD VDD Operating Voltage Operating Current (Crystal OSC) Operating Current (RC OSC) Operating Current (Crystal OSC, RC OSC) Standby Current (WDT Enabled) Standby Current (WDT Disabled) Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset I/O Port Sink Current (PA, PD, PE) I/O Port Source Current (PA, PC, PD) PC Ports Sink Current for LED Driver PE Ports Source Current for LED Driver Pull-high Resistance 5V VAD A/D Input Voltage 3/4 3/4 3/4 3V 5V 3V 5V 5V 3V 5V 3V 5V 3/4 3/4 3/4 3/4 3/4 3V 5V 3V 5V 3V 5V 3V 5V 3V Operating Temperature: 40C~+85C, Ta=25C Test Conditions Min. Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz ADC disable No load, fSYS=4MHz ADC disable No load, fSYS=8MHz ADC disable No load, system HALT No load, system HALT 3/4 3/4 3/4 3/4 3/4 VOL=0.1VDD VOL=0.1VDD VOH=0.9VDD VOH=0.9VDD VOL=0.1VDD VOL=0.1VDD VOH=0.9VDD VOH=0.9VDD 3/4 3/4 3/4 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 2.7 4 10 -2 -5 8 20 -4 -10 20 10 0 3/4 3/4 0.6 2 0.8 2.5 4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3.0 8 20 -4 -10 16 40 -8 -20 60 30 3/4 5.5 5.5 1.5 4 1.5 4 8 5 10 1 2 0.3VDD VDD 0.4VDD VDD 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 100 50 VDD V V mA mA mA mA mA mA mA mA mA V V V V V mA mA mA mA mA mA mA mA kW kW V Typ. Max. Unit IDD1 IDD2 IDD3 ISTB1 ISTB2 VIL1 VIH1 VIL2 VIH2 VLVR IOL1 IOH1 IOL2 IOH2 RPH Rev. 1.00 4 December 21, 2006 HT46R322/HT46R342 Test Conditions Symbol Parameter VDD IADC DNL INL Additional Power Consumption if A/D Converter is Used ADC Differential Non-Linearity ADC Integral Non-Linearity 3V 5V 5V 5V 3/4 tAD=1ms tAD=1ms 3/4 Conditions 3/4 3/4 3/4 3/4 3/4 3/4 0.5 1.5 3/4 2.5 3/4 1 3 2 4 12 mA mA mA mA Bits Min. Typ. Max. Unit RESOLU Resolution A.C. Characteristics Test Conditions Symbol Parameter VDD fSYS System Clock (Crystal OSC, RC OSC) Timer I/P Frequency (TMR) Watchdog Oscillator Period 5V tWDT1 tWDT2 tRES tSST tLVR tINT tAD tADC tADCS Watchdog Time-out Period (WDT OSC) Watchdog Time-out Period (System Clock) External Reset Low Pulse Width System Start-up Timer Period Low Voltage Width to Reset Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3V Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 3/4 3/4 Wake-up from HALT 3/4 3/4 3/4 3/4 3/4 400 400 0 0 45 32 215 217 1 3/4 0.25 1 1 3/4 3/4 3/4 3/4 3/4 3/4 90 65 3/4 3/4 3/4 1024 1 3/4 3/4 80 32 4000 8000 4000 8000 180 130 216 218 3/4 3/4 2 3/4 3/4 3/4 3/4 Min. Typ. Max. Ta=25C Unit kHz kHz kHz kHz ms ms tWDTOSC tSYS ms *tSYS ms ms ms tAD tAD fTIMER tWDTOSC Note: *tSYS=1/fSYS Rev. 1.00 5 December 21, 2006 HT46R322/HT46R342 OP Amplifier Electrical Characteristics Test Conditions Symbol Parameter VDD D.C. Electrical Characteristic VDD VOPOS1 VOPOS2 VCM PSRR CMRR tRES Operating Voltage Input Offset Voltage Input Offset Voltage Common Mode Voltage Range Power Supply Rejection Ratio Common Mode Rejection Ratio Response Time (Comparator) 3/4 5V 5V 3/4 3/4 5V 3/4 3/4 3/4 By Calibration 3/4 3/4 VCM=0~VDD-1.4V Input overdrive=10mV 3 -10 -2 VSS 60 60 3/4 3/4 3/4 3/4 3/4 80 80 3/4 5.5 10 2 VDD1.4V 3/4 3/4 2 V mV mV V dB dB ms Conditions Min. Typ. Max. Unit Ta=25C A.C. Electrical Characteristic VOPOS1 SR GBW Open Loop Gain Slew Rate +, Slew Rate Gain Band Width 3/4 3/4 3/4 No load RL=1M, CL=100p 3/4 60 3/4 3/4 80 0.1 3/4 3/4 3/4 100 dB V/ms kHz Rev. 1.00 6 December 21, 2006 HT46R322/HT46R342 Functional Description Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter controls the sequence in which the instructions stored in program memory are executed and whose contents specify full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter, PCL, is a readable and writeable register. Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. S y s te m O S C 2 (R C C lo c k o n ly ) PC PC PC+1 PC+2 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Mode Initial Reset External Interrupt Timer/Event Counter Overflow A/D Converter Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine Program Counter *11 0 0 0 0 *10 0 0 0 0 *9 0 0 0 0 *8 0 0 0 0 *7 0 0 0 0 *6 0 0 0 0 *5 0 0 0 0 *4 0 0 0 0 *3 0 0 1 1 *2 0 1 0 1 *1 0 0 0 0 *0 0 0 0 0 Program Counter+2 *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 Program Counter Note: PC11~PC8: Current Program Counter bits S11~S0: Stack register bits #11~#0: Instruction Code bits @7~@0: PCL bits For the HT46R322 device the Program Counter is 11 bits wide, i.e. from b10~b0, therefore the b11 column in the table is not applicable. 7 December 21, 2006 Rev. 1.00 HT46R322/HT46R342 Program Memory - ROM The program memory is used to store the program instructions which are to be executed as well as table data and interrupt entries. It is structured into 2K14 bits for the HT46R322 device and 4K x 15 bits for the HT46R342 device, which can be addressed by both the program counter and table pointer. Certain locations in the program memory are reserved for use by the reset and by the interrupt vectors. * Location 000H 000H 004H 008H 00CH D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e A /D C o n v e r te r In te r r u p t S u b r o u tin e P ro g ra m M e m o ry n00H nFFH L o o k - u p T a b le ( 2 5 6 w o r d s ) This vector is reserved for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. * Location 004H 700H 7FFH L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 4 b its N o te : n ra n g e s fro m 0 to 7 This vector is used by the external interrupt INT. If the external interrupt pin on the device receives a low going edge, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. * Location 008H Program Memory - HT46R322 000H 004H 008H 00CH D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e A /D C o n v e r te r In te r r u p t S u b r o u tin e P ro g ra m M e m o ry n00H nFFH This vector is used by the Timer/Event Counter. If a timer overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. * Location 00CH This vector is used by the A/D converter. When an A/D cycle conversion is complete, the program will jump to this location and begin execution if the A/D interrupt is enabled and the stack is not full. * Table location L o o k - u p T a b le ( 2 5 6 w o r d s ) Any location in the Program Memory space can be used as a look-up table. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH. Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining bits are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register, which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH register is read only and cannot be F00H FFFH L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 5 b its N o te : n ra n g e s fro m 0 to F Program Memory - HT46R342 restored. If the main routine and the ISR, Interrupt Service Routine, both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used Instruction TABRDC [m] TABRDL [m] Table Location *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0 Table Location Note: *11~*0: Table location bits P11~P8: Current program counter bits @7~@0: Table pointer bits For the HT46R322 device the Table address is 11 bits wide, i.e. from b10~b0, therefore the b11 column in the table is not applicable. 8 December 21, 2006 Rev. 1.00 HT46R322/HT46R342 in the ISR. In such a case errors can occur. Therefore, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be used in both the main routine and the ISR, the interrupt is should be disabled prior to the table read instruction. It should not be re-enabled until the TBLH has been backed up. All table related instructions require two cycles to complete their operation. These areas may function as normal program memory depending upon requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 6 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer, known as stack pointer, and is also neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the program counter is restored to its previous value from the stack. After a device reset, the stack pointer will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented, using a RET or RETI instruction, the interrupt will be serviced. This feature prevents a stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost. Only the most recent 6 return addresses are stored. Data Memory - RAM The data memory has a structure of 1158 bits for the HT46R322 device and 2198 bits for the HT46R342 device. The data memory is divided into two functional groups: special function registers and general purpose data memory. The general purpose memory has a structure of 888 bits for the HT46R322 device and 192bits8 bits for the HT46R342 device. Most locations are read/write, but some are read only. The remaining space between the end of the Special Purpose Data Memory and the beginning of the General Purpose Data Memory is reserved for future expanded usage, reading these locations will obtain a result of 00H. The general purpose data memory, addressed from 28H to 7FH in the HT46R322, and from 40H to FFH in the HT46R342, is used for user data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can Rev. 1.00 9 be set and reset by the SET [m].i and CLR [m].i instructions. They are also indirectly accessible through memory pointer register, MP. 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H OPAC ADRL ADRH ADCR ACSR H T 4 6 R 3 2 2 /H T 4 6 R 3 4 2 24H 27H 28H 24H 39H 40H :U nused R e a d a s "0 0 " PA PAC PB PBC PC PCC PD PDC PE PEE PW M0 PW M1 S p e c ia l P u r p o s e D a ta M e m o ry TM R TM RC STATUS IN T C ACC PCL TBLP TBLH In d ir e c t A d d r e s s in g R e g is te r MP 7FH G e n e ra l P u rp o s e D a ta M e m o ry (8 8 B y te s ) H T46R 322 FFH G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s ) H T46R 342 RAM Mapping Indirect Addressing Register Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation on [00H] accesses data memory pointed to by the MP register. Reading location 00H itself indirectly will return the result 00H. Writing indirectly results in no operation. For the HT46R322 device the memory pointer register, MP, is a 7-bit register, while for the HT46R342 device it is an 8-bit register. For the HT46R322 device, bit 7 of MP is undefined and if read will return the result 1, any write operation will only transfer the lower 7-bits of data to MP. Accumulator The accumulator is closely related to ALU operations and can carry out immediate data operations. Any data movement between two data memory locations must pass through the accumulator. December 21, 2006 HT46R322/HT46R342 Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions: * Arithmetic operations - ADD, ADC, SUB, SBC, DAA * Logic operations - AND, OR, XOR, CPL * Rotation - RL, RR, RLC, RRC * Increment and Decrement - INC, DEC * Branch decision - SZ, SNZ, SIZ, SDZ .... tion operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The devices provide an external interrupt, an internal timer/event counter interrupt and an A/D converter interrupt. The Interrupt Control Register, INTC, contains the interrupt control bits to set the enable or disable and the interrupt request flags. The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addiBit No. 0 Label C Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register 1 2 3 4 5 6, 7 AC Z OV PDF TO 3/4 Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI ETI EADI EIF TF ADF 3/4 Function Controls the master (global) interrupt (1=enabled; 0=disabled) Controls the external interrupt (1=enabled; 0=disabled) Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled) Controls the A/D converter interrupt (1=enabled; 0=disabled) External interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter request flag (1=active; 0=inactive) A/D converter request flag (1=active; 0=inactive) Unused bit, read as 0 INTC (0BH) Register Rev. 1.00 10 December 21, 2006 HT46R322/HT46R342 Once an interrupt subroutine is serviced, all the other interrupts will be blocked by clearing the EMI bit. This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit in INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. All interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a high to low transition on the INT pin, which will set the related interrupt request flag, EIF, which is bit 4 of INTC. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag, EIF, and EMI bits will be cleared to disable other interrupts. The internal timer/event counter interrupt is initialised by setting the timer/event counter interrupt request flag, TF, which is bit 5 of INTC, caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag, TF, will be reset and the EMI bit cleared to disable further interrupts. The A/D converter interrupt is initialised by setting the A/D converter request flag, ADF, which is bit 6 of INTC, caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag, ADF, will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1. Of course, the stack must not be full. To return from the interrupt subroutine, a RET or RETI instruction may be executed. A RETI instruction will set the EMI bit to enable an interrupt service, but a RET instruction will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External Interrupt Timer/Event Counter Overflow A/D Converter Interrupt Priority 1 2 3 Vector 004H 008H 00CH Once the interrupt request flags, TF, EIF, ADF, are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator Configuration There are two oscillator circuits in the microcontroller, namely an RC oscillator and a crystal oscillator, the choice of which is determined by a configuration option. When the system enters the Power-down mode the system oscillator stops and ignores external signals to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VSS is required whose resistance value must range from 24kW to 1MW. The system clock, divided by 4, can be monitored on pin OSC2 if a pull-high resistor is connected. This signal can be used to synchronise external logic. The RC oscillator provides the most cost effective solution, however the frequency of oscillation may vary with VDD, temperature and the process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator; no other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required, If the oscillating frequency is less than 1MHz. The WDT oscillator is a free running on-chip RC oscillator, and requires no external components. Even if the system enters the power down mode, the system clock V OSC1 DD 470pF OSC1 OSC2 C r y s ta l O s c illa to r fS YS /4 RC OSC2 O s c illa to r System Oscillator 11 December 21, 2006 Rev. 1.00 HT46R322/HT46R342 is stopped, but the WDT oscillator keeps running with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by a configuration option to conserve power. Watchdog Timer - WDT The WDT clock source comes from either its own integrated RC oscillator, known as the WDT oscillator, or the instruction clock, which is the system clock divided by 4. The choice of which one is used is decided by a configuration option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by a configuration option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with a period of 65ms at 5V nominal) is selected, it is divided by 32768~65536 to get a time-out period of approximately 2.1s~4.3s. This time-out period may vary with temperatures, VDD and process variations. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the Power-down state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT instruction will stop the system clock. The WDT overflow under normal operation will initialise a chip reset and set the status bit TO. But in the Power-down mode, the overflow will initialisze a warm reset, and only the program counter and SP are reset to zero. To clear the contents of the WDT, three methods are adopted; external reset (a low level on the RES pin), a software instruction and a HALT instruction. The software instruction include CLR WDT and the other set CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the configuration option - CLR WDT times selection op tion. If the CLR WDT is selected (i.e. CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. CLR WDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Power Down Operation - HALT The HALT mode is initialised by the HALT instruction and results in the following... * The system oscillator will be turned off but the WDT oscillator keeps running (if the WDT oscillator is selected). * The contents of the on chip Data Memory and regis- ters remain unchanged. * WDT will be cleared and start counting again (if the WDT clock is from the WDT oscillator). * All of the I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialisation and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the reason for the chip reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and Stack Pointer; the others keep their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by the options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two sequences may happen. If the related interrupt is dis- S y s te m C lo c k /4 O p tio n S e le c t W DT OSC fS 8 - b it C o u n te r 7 - b it C o u n te r T T W D T T im e - o u t 15 16 fS /2 ~ fS /2 CLR W DT Watchdog Timer Rev. 1.00 12 December 21, 2006 HT46R322/HT46R342 abled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimise power consumption, all the I/O pins should be carefully managed before entering the status. Reset There are three ways in which a reset can occur: * RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation V DD The functional unit chip reset status are shown below. Program Counter Interrupt WDT 000H Disable Clear. After master reset, WDT begins counting Timer/Event Counter Off Input/Output Ports Stack Pointer Input mode Points to the top of the stack VDD RES S S T T im e - o u t C h ip R eset tS ST Reset Timing Chart The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the program counter and stack pointer, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT W DT RES 0 .0 1 m F * 100kW RES 10kW 0 .1 m F * Reset Circuit Note: * Ensure that the length of the wiring, which is connected to the RES pin is as short as possible, to avoid noise interference. HALT W a rm R eset Note: u means unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). OSC1 SST 1 0 - b it R ip p le C o u n te r S y s te m R eset C o ld R eset Reset Configuration Rev. 1.00 13 December 21, 2006 HT46R322/HT46R342 The registers states are summarised in the following table. Register MP - HT46R322 MP - HT46R342 ACC PCL TBLP TBLH - HT46R322 TBLH - HT46R342 STATUS INTC TMR TMRC PA PAC PB PBC PC PCC PD PDC PE PEC PWM0 PWM1 OPAC ADRL ADRH ADCR ACSR Note: Reset (Power On) 1xxx xxxx xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx --xx xxxx -xxx xxxx --00 xxxx -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx 0000 1000 xxxx ---xxxx xxxx 0100 0000 1--- --00 * stands for warm reset u stands for unchanged x stands for unknown WDT Time-out (Normal Operation) 1uuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu -uuu uuuu --1u uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx 0000 1000 xxxx ---xxxx xxxx 0100 0000 1--- --00 RES Reset (Normal Operation) 1uuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu -uuu uuuu --uu uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx 0000 1000 xxxx ---xxxx xxxx 0100 0000 1--- --00 RES Reset (HALT) 1uuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu -uuu uuuu --01 uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx 0000 1000 xxxx ---xxxx xxxx 0100 0000 1--- --00 WDT Times-out (HALT)* 1uuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu -uuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---uuuu uuuu uuuu uuuu u--- --uu Rev. 1.00 14 December 21, 2006 HT46R322/HT46R342 Timer/Event Counter A timer/event counter is implemented in the microcontroller. The timer/event counter contains an 8-bit programmable count-up counter whose clock source may come from an external source or from the system clock. Using an external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. The timer/event counter can generate a PFD signal by using the external or internal clock. The PFD frequency is determined by the equation fINT/[2(256-N)]. There are 2 registers related to the timer/event counter; TMR and TMRC. Two physical registers are mapped to the TMR location. Writing to TMR places the start value in the timer/event counter preload register, while reading TMR retrieves the contents of the timer/event counter. The TMRC register is a timer/event counter control register, which defines some options. The TM0 and TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source emanates from the external TMR pin. The timer mode functions as a normal timer with the clock source coming from the fINT clock. The pulse width measurement mode can be used to count the high or low level duration of the external signal on TMR. The counting is based on fINT. Bit No. Label In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register and generates an interrupt request flag, TF, which is bit 5 of INTC, at the same time. In the pulse width measurement mode with the TON and TE bits equal to one, once TMR has received a transient from low to high (or high to low if the TE bits is 0) it will start counting until TMR returns to the original level and resets the TON bit. The measured result will remain in the timer/event counter even if the activated transient occurs again. Therefore only a one cycle measurement is made. Not until the TON bit is once again set, will the cycle measurement function again if further transient pulses are received. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit,TON, which is bit 4 of TMRC, should be set to 1. In the pulse width measurement mode, the TON bit will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON bit can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the interrupt service. Function Defines the prescaler stages, PSC2, PSC1, PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR active edge of the timer/event counter: In Event Counter Mode (TM1,TM0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (TM1,TM0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable or disable the timer counting (0=disable; 1=enable) Unused bits, read as 0 Defines the operating mode (TM1, TM0)= 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC (0EH) Register 0 1 2 PSC0 PSC1 PSC2 3 TE 4 5 TON 3/4 TM0 TM1 6 7 Rev. 1.00 15 December 21, 2006 HT46R322/HT46R342 PW M (6 + 2 ) C o m p a re fS YS T o P D 0 C ir c u it 8 - s ta g e P r e s c a le r 8 -1 M U X PSC2~PSC0 TM R TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - B it T im e r /E v e n t C o u n te r 1 /2 O v e r flo w to In te rru p t PFD f IN T D a ta B u s TM 1 TM 0 8 - B it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d Timer/Event Counter In the case of a timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. The timer/event counter will still operate until an overflow occurs. When the timer/event counter is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the programmer. Bit0~bit2 of the TMRC register can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. The definitions are as shown. The overflow signal of timer/event counter can be used to generate the PFD signal. Input/Output Ports There are 19 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC, PD and PE, which are mapped to the data memory of [12H], [14H], [16H], [18H] and [1AH] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H, 18H or 1AH). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC, PEC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. V C o n tr o l B it D a ta B u s D CK S Q W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r Q P u ll- H ig h O p tio n PA0 PA3 PA4 PA5 PA6 PB0 PB4 PC0 PD0 PD1 PD2 PE0 M U X PFDEN (P A 3 ) U X W a k e - u p o p tio n ~PA2 /P F D /T M R /IN T ,PA7 /A N 0 ~ P B 3 /A N 3 ~PB7 ~PC7 /P W M 0 /P W M 1 ,PD 3 ~PE7 DD D a ta B it D Q CK S Q W r ite D a ta R e g is te r (P D 0 o r P W M ) PA3 PFD M R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly ) IN T fo r P A 5 O n ly TM R fo r P A 4 O n ly Input/Output Ports Rev. 1.00 16 December 21, 2006 HT46R322/HT46R342 After a device reset, the input/output lines will default to inputs and remain at a high level or floating state, dependent upon the pull-high configuration options. Each bit of these input/output latches can be set or cleared by the SET [m].i and CLR [m].i (m=12H, 14H, 16H, 18H or 1AH) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each I/O line has a pull-high option. Once the pull-high configuration option is selected, the I/O line has a pull-high resistor, otherwise, theres none. Take note that a non-pull-high I/O line operating in input mode will cause a floating state. Pin PA3 is pin-shared with the PFD signal. If the PFD configuration option is selected, the output signal in the output mode for PA3 will be the PFD signal generated by the timer/event counter overflow signal. The input mode always retains its original functions. Once the PFD option is selected, the PFD output signal is controlled by the PA3 data register only. Writing a 1 to the PA3 data register will enable the PFD output function and writing 0 will force the PA3 to remain at 0. The I/O functions for PA3 are shown below. I/O Mode PA3 Note: I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PFD) Logical Input O/P (PFD) PFD (Timer on) It is recommended that unused I/O lines should be setup as output pins by software instructions to avoid consuming power under input floating states. PWM The microcontroller provides a 2 channel (6+2) bits PWM0/PWM1 output shared with PD0/PD1. The PWM channel has its data register denoted as PWM0 and PWM1. The frequency source of the PWM counter comes from fSYS. The PWM register is an eight bit register. Once PD0/PD1 are selected as PWM outputs and the output function of PD0/PD1 is enabled (PDC.0=0 or PDC.1=0), writing a 1 to the PD0/PD1 data register will enable the PWM output function while writing a 0 will force the PD0/PD1 outputs to stay at 0. A PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. Group 2 is denoted by AC which is the value of PWM.1~PWM.0. In a PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter AC (0~3) i The PFD frequency is the timer/event counter overflow frequency divided by 2. Pins PA5 and PA4 are pin-shared with INT and TMR pins respectively. The PB can also be used as A/D converter inputs. The A/D function will be described later. There are two PWM functions shared with pins PD0 and PD1. If the PWM functions are enabled, the PWM signals will appear on PD0 and PD1, the pins are setup as outputs. Writing a 1 to the PD0 or PD1 data register will enable the PWM outputs to function while writing a 0 will force the PD0 and PD1 outputs to remain at 0. The I/O functions of PD0 and PD1 are as shown. I/O Mode PD0 PD1 I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PWM) Logical Input O/P (PWM) PWM0 PWM1 PC 0~PC 7 PE0~PE7 H T -M C U L E D D is p la y 8 x 8 A rra y Rev. 1.00 17 December 21, 2006 HT46R322/HT46R342 fS YS /2 [P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0 YS 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 M o d u la tio n c y c le 1 PW M 2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS YS 2 5 /6 4 M o d u la tio n c y c le 3 2 6 /6 4 M o d u la tio n c y c le 0 PWM A/D Converter A 4 channel 12-bit resolution A/D converter is implemented in the microcontrollers. The reference voltage for the A/D is VDD. The A/D converter contains 4 special registers, which are; ADRL, ADRH, ADCR and ACSR. The ADRH and ADRL registers are the A/D conversion result register higher-order byte and lower-order byte and are read-only. After the A/D conversion has completed, the ADRL and ADRH registers should be read to get the conversion result data. The ADCR register is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. It is used to start an A/D conversion, define the PB configuration, select the converted analog channel, and give the START bit a raising edge and a falling edge (0(R)1(R)0). At the end of an A/D conversion, the EOCB bit is cleared and an A/D converter interrupt occurs, if the A/D converter interrupt is enabled. The ACSR register is an A/D clock setting register, which is used to select the A/D clock source. The A/D converter control register is used to control the A/D converter. Bit2~bit0 of the ADCR regsiter are used to select an analog input channel. There are a total of four channels to select. Bit5~bit3 of the ADCR register are used to set the PB configurations. PB can be configured as an analog input or as a digital I/O line decided by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled, and the A/D converter circuit is powered on. The EOCB bit, bit6 of ADCR, is the end of A/D conversion flag. This bit is monitored to check when the A/D conversion has completed. The START bit of the ADCR register is used to initiate the A/D conversion process. When the START bit is provided with a raising edge and then a falling edge, the A/D conversion process will begin. In order to ensure that the A/D conversion is completed, the START should remain at 0 until the EOCB flag is cleared to 0 which indicates the end of the A/D conversion. Bit 7 of the ACSR register is used for test purposes only and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are used to select the A/D clock source. When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to 1 when the START bit is set from 0 to 1. Important Note for A/D initialisation: Special care must be taken to initialise the A/D converter each time the Port B A/D channel selection bits are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialisation is implemented by setting the START bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel selection bits are all cleared to zero then an A/D initialisation is not required. Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADRL ADRH Note: D3 D2 D1 D0 D8 3/4 D7 3/4 D6 3/4 D5 3/4 D4 D11 D10 D9 D0~D11 is A/D conversion result data bit LSB~MSB. ADRL (20H), ADRH (21H) Register Rev. 1.00 18 December 21, 2006 HT46R322/HT46R342 Bit No. Label ACS2, ACS1, ACS0: Select A/D channel 0, 0, 0: AN0 0, 0, 1: AN1 0, 1, 0: AN2 0, 1, 1: AN3 1, X, X: undefined, cannot be used Unused bit, read as 0. PCR2, PCR1, PCR0: PB3~PB0 configurations 0, 0, 0: PB3 PB2 PB1 PB0 (The ADC circuit is power off to reduce power consumption.) 0, 0, 1: PB3 PB2 PB1 AN0 0, 1, 0: PB3 PB2 AN1 AN0 0, 1, 1: PB3 AN2 AN1 AN0 1, x, x: AN3 AN2 AN1 AN0 Indicates end of A/D conversion. (0 = end of A/D conversion) Each time bits 3~5 change state the A/D should be initialised by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See Important note for A/D initialisation. Function 0 1 2 ACS0 ACS1 ACS2 2 3/4 3 4 5 PCR0 PCR1 PCR2 6 7 EOCB START Starts the A/D conversion. (0(R)1(R)0= start; 0(R)1= Reset A/D converter and set EOCB to 1) ADCR (22H) Register Bit No. Label Select the A/D converter clock source. 0, 0: fSYS/2 ADCS0 0, 1: fSYS/8 ADCS1 1, 0: fSYS/32 1, 1: Undefined 3/4 TEST Unused bit, read as 0. For internal test only. Function 0 1 2~6 7 ACSR (23H) Register M in im u m START o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d EOCB PC R2~ PCR0 A /D tA 000B DCS s a m p lin g tim e A /D tA DCS s a m p lin g tim e A /D s a m p lin g tim e tA D C S 101B 000B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n 100B 100B AC S2~ ACS0 000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D N o te : A /D c lo c k m u s t b e fS tA D C S = 3 2 tA D tA D C = 8 0 tA D YS 010B S ta rt o f A /D c o n v e r s io n 000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n 001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n d o n 't c a r e E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e tA D C c o n v e r s io n tim e YS tA D C A /D c o n v e r s io n tim e A /D /2 , fS /8 o r fS YS /3 2 A/D Conversion Timing Rev. 1.00 19 December 21, 2006 HT46R322/HT46R342 The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using EOCB Polling Method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs mov ADCR,a ; and select AN0 to be connected to the A/D converter : : ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START ; reset A/D clr START ; start A/D Polling_EOC: sz EOCB ; poll the ADCR register EOCB bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a,ADRH ; read conversion result high byte value from the ADRH register mov adrh_buffer,a ; save result to user defined memory mov a,ADRL ; read conversion result low byte value from the ADRL register mov adrl_buffer,a ; save result to user defined memory : : jmp start_conversion ; start next A/D conversion Example: using interrupt method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov mov a,00100000B ADCR,a : ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START clr START clr ADF set EADI set EMI : : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a mov a,STATUS mov status_stack,a : : mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a clr START set START clr START : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a mov a,acc_stack reti Rev. 1.00 ; reset A/D ; start A/D ; clear ADC interrupt request flag ; enable ADC interrupt ; enable global interrupt ; save ACC to user defined memory ; save STATUS to user defined memory ; read conversion result high byte value from the ADRH register ; save result to user defined register ; read conversion result low byte value from the ADRL register ; save result to user defined register ; reset A/D ; start A/D ; restore STATUS from user defined memory ; restore ACC from user defined memory 20 December 21, 2006 HT46R322/HT46R342 Low Voltage Reset - LVR The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as what happens when changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: * The low voltage (0.9V~VLVR) has to remain in its origi- The relationship between VDD and VLVR is shown below. VDD 5 .5 V V OPR 5 .5 V V 3 .0 V 2 .2 V LVR nal state to exceed tLVR. If the low voltage state does not exceed tLVR, the LVR will ignore it and will not perform a reset function. * The LVR uses the OR function with the external RES 0 .9 V Note: signal to perform a chip reset. V 5 .5 V DD VOPR is the voltage range for proper chip operation at 4MHz system clock. V LVR LVR D e te c t V o lta g e 0 .9 V 0V R e s e t S ig n a l R eset *1 N o r m a l O p e r a tio n *2 R eset Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilised, the SST provides an extra delay of 1024 system clock pulses before beginning normal operation. *2: Since the low voltage has to maintain in its original state and exceed tLVR, therefore tLVR delay enter the reset mode. OP Amplifier/Comparator The devices include an integrated operational amplifier or comparator, selectable via configuration option. The default is function is comparator. The input voltage offset is adjustable by using a common mode input to calibrate the offset value. APN VR APP APO The calibration process is as follows: APN APP S1 S2 APO S3 * Set bit AOFM=1 to select the offset cancellation mode - this closes switch S3 * Set the ARS bit to select which input pin is the reference voltage - closes either switch S1 or S2 * Adjust bits AOF0~AOF3 until the output status OPAOP has changed. * Set AOFM=0 to select the normal operating mode Rev. 1.00 21 December 21, 2006 HT46R322/HT46R342 Bit No. 0 1 2 3 4 Label AOF0 AOF1 AOF2 AOF3 ARS Function OP amp/comparator input offset voltage cancellation control bits OP amp/comparator input offset voltage cancellation reference selection bit 1/0 : select OPP/OPN (CP/CN) as the reference input Input offset voltage cancellation mode and OP amp/comparator mode selection 1: input offset voltage cancellation mode 0: OP amp/comparator OP amp/comparator output; positive logic OP amp/comparator enable/disable (1/0) If OP/comparator is disabled, output is floating. OPAC (1FH) Register 5 6 7 AOFM OPAOP OPAEN If the OP amp/comparator is disabled, the power consumption will be very small. To ensure that power consumption is minimised when the device is in the Power-down mode, the OP amp/comparator should be switched off by clearing bit OPAEN to 0 before entering the Power-down mode. Configuration Options The following table shows the various microcontroller configuration options. All of the configuration options must be properly defined to ensure correct system functioning. No. 1 2 3 4 5 6 7 8 9 10 WDT clock source: WDTOSC or T1 (fSYS/4) WDT function: enable or disable CLRWDT instruction(s): one or two clear WDT instruction(s) System oscillator: RC or crystal Pull-high resistors (PA, PB, PD): none or pull-high PWM enable or disable PA0~PA7 wake-up: enable or disable PFD enable or disable Low voltage reset selection: enable or disable LVR function. Comparator or OP selection Options Rev. 1.00 22 December 21, 2006 HT46R322/HT46R342 Application Circuits V PA0~PA2 0 .0 1 m F * 100kW 0 .1 m F 10kW DD VDD RES P A 3 /P F D P A 4 /T M R P A 5 /IN T PA6~PA7 P B 0 /A N 0 ~ P B 3 /A N 3 PB4~PB7 PC PD0 PD1 PD 0~ /P W /P W 2, PC M M PD APN APP APO 7 1 0 3 V DD 470pF R OSC OSC1 fS YS R C S y s te m O s c illa to r 24kW /4 OSC2 OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r C1 OSC C ir c u it S e e R ig h t S id e OSC1 OSC2 PE0~PE7 C2 R1 OSC2 OSC H T 4 6 R 3 2 2 /H T 4 6 R 3 4 2 C ir c u it The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) HT46R322 Crystal or Resonator C1, C2 8MHz Crystal 8MHz Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal & Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator 400kHz Resonator 10pF 10pF 25pF 10pF 25pF 10pF 30pF 68pF 300pF 300pF 300pF 300pF R1 4.3kW 4.7kW 12kW 12kW 12kW 12kW 12kW 18kW 10kW 10kW 10kW 10kW C1, C2 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD R1 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD HT46R342 The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.00 23 December 21, 2006 HT46R322/HT46R342 Instruction Set Summary Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z Rev. 1.00 24 December 21, 2006 HT46R322/HT46R342 Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected (1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (2) (3) (1) (4) Rev. 1.00 25 December 21, 2006 HT46R322/HT46R342 Instruction Definition ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m] Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m] Rev. 1.00 26 December 21, 2006 HT46R322/HT46R342 AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m] Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m] Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.00 27 December 21, 2006 HT46R322/HT46R342 CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0 Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) CLR WDT1 Description Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CLR WDT2 Description Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CPL [m] Description Operation Affected flag(s) Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Rev. 1.00 28 December 21, 2006 HT46R322/HT46R342 CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Operation Affected flag(s) Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) DEC [m] Description Operation Affected flag(s) Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 DECA [m] Description Operation Affected flag(s) Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Rev. 1.00 29 December 21, 2006 HT46R322/HT46R342 HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1 Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1 Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m] Rev. 1.00 30 December 21, 2006 HT46R322/HT46R342 MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m] Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] Rev. 1.00 31 December 21, 2006 HT46R322/HT46R342 RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RETI Description Operation Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RL [m] Description Operation Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RLA [m] Description Operation Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.00 32 December 21, 2006 HT46R322/HT46R342 RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Affected flag(s) Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) RR [m] Description Operation Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RRA [m] Description Operation Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RRC [m] Description Operation Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Affected flag(s) Rev. 1.00 33 December 21, 2006 HT46R322/HT46R342 RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SDZA [m] Description Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) Rev. 1.00 34 December 21, 2006 HT46R322/HT46R342 SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1 Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SIZA [m] Description Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SNZ [m].i Description Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0 Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.00 35 December 21, 2006 HT46R322/HT46R342 SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1 Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1 Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1 Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4 Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.00 36 December 21, 2006 HT46R322/HT46R342 SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZ [m].i Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0 Operation Affected flag(s) TO 3/4 TABRDC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) TABRDL [m] Description Operation Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.00 37 December 21, 2006 HT46R322/HT46R342 XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m] Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m] Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x Rev. 1.00 38 December 21, 2006 HT46R322/HT46R342 Package Information 44-pin QFP (1010) Outline Dimensions C D G 23 I 34 22 L F A B E 44 12 K 1 11 a J 33 H Symbol A B C D E F G H I J K L a Dimensions in mm Min. 13 9.9 13 9.9 3/4 3/4 1.9 3/4 0.25 0.73 0.1 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.8 0.3 3/4 3/4 3/4 3/4 3/4 0.1 3/4 Max. 13.4 10.1 13.4 10.1 3/4 3/4 2.2 2.7 0.5 0.93 0.2 3/4 7 Rev. 1.00 39 December 21, 2006 HT46R322/HT46R342 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holmate.com Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 40 December 21, 2006 |
Price & Availability of HT46R342
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |